XMP compatibility
Early BIOSes of the test motherboard Asus Maximus Z790 Hero unfortunately cannot handle the modules and the board gets stuck during post after actually successful memory training and Qcode “55”. After an update to 2301, however, it works immediately and stably with “XMP II”, i.e. XMP profile including subtimings. The timings are conservative, as you would expect for an XMP kit with these clock rates, but are perfectly usable and at least faster than JEDEC.
Overclocking
But how does Samsung’s latest DDR5 variant clock? In short: not great. DDR5-6800 was the maximum stable clock, at least with the current BIOS version. But even to achieve this rather mediocre clock rate, you have to dig deep into the tuning box of tricks. MCH Fullcheck Enabled, as well as manually loosened activate timings tRRD_sg/_dg and tRDRD_dg and tWRWR_dg of 11 each are absolutely necessary, so that more than 6400 Mbps can even be booted.
![](https://www.igorslab.de/wp-content/uploads/2024/08/Screenshot-2024-07-16-000250-980x551.png)
With “Auto”, the Asus BIOS leaves MCH Full Check disabled sets the activate timings to 8. This also works well with the vast majority of current DDR5 ICs, but not with Samsung 16 Gbit S-Die. At least not if you want to tease out the maximum clock rate in July 2024.
A slight scaling with the operating voltages can be observed, not only with tCL, but also with tRCD, but the jump from 1.35 V in the XMP to the maximum of 1.435 V makes up a tick here at most. tCL 42, tRCD 45, tRP 42 and tRAS 70 with DDR5-6800 is really no reason for dancing for joy. The consistently mediocre subtimings can’t save the Samsung 16 Gbit S-Die either and thus the performance is likely to be rather mediocre. More on this in the benchmarks.
![](https://www.igorslab.de/wp-content/uploads/2024/08/Screenshot-2024-08-01-014607-980x551.png)
In fact, the performance loss due to the activate timings from 8 to 11 was so big that I also tried a more conservative config with the maximum clock rate at which tRRD_dg 8 still works: DDR5-6133. From here, I only increase the voltage to 1.435 V and tighten the remaining timings as much as possible. tWR / tWRPRE at Auto and tREFI at 16383 unfortunately have to remain so loose, but with the other timings tightened a little performance can still be gained.
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