What does dynamic pSLC cache actually mean?
Now we come to a more technical detail, which most people might not be aware of to the full extent. A lot has already been written about pSLC cache, so there’s no need to go through it again in detail, at most as a small refresher. Here we go…
To increase the write speed, the so-called “pseudo-SLC cache” (pSLC) is often used in consumer products, although it can now also be found in various industrial solutions. For this, part of the NAND capacity is configured as SLC memory, in which only one bit per cell is stored. Accordingly, this memory can be written and read very quickly. Since it is not dedicated, i.e. not a real SLC memory, it is called pseudo SLC. Such a cache can be used for all memory types that store several bits per flash cell, i.e. three bits as here with TLC. The pSLC cache also uses a significantly higher voltage for the one bit, which provides a certain level of security and is therefore better than Fast Page.
The use of pSLC cache offers a speed advantage, especially when the storage medium is not busy with read or write accesses between writing larger amounts of data. This idle time is used by the storage medium to move data from the cache to the TLC area.
![](https://www.igorslab.de/wp-content/uploads/2021/08/Scheme-01-pSLC-Cache.jpg)
But everyone knows the disadvantages of the pSLC. When the fast pSLC cache is full, the speed drops significantly because further write accesses to the storage medium must first free the pSLC by moving older data from the cache to the TLC memory.
But what is the meaning of “dynamic pSLC cache”? Dynamic pSLC cache has now also found its way into industrial memory solutions, but only with very hard restrictions. In contrast to the static pSLC cache, up to 100 es of NAND flash are used dynamically as pSLC cache, depending on how full the storage medium is. The cache can therefore cover up to 1/3 of the total memory size
However, the write speed of the storage medium depends not only on the amount of data that is written without interruption, but also on the fill level of the memory. And this is exactly what makes the write speed in the life cycle difficult to predict.
![](https://www.igorslab.de/wp-content/uploads/2021/08/Scheme-02-Dynamic-pSLC-Cache.jpg)
Although NAND flash manufacturers advise against dynamically changing the configuration of flash blocks as pSLC or TLC memory for reasons of reliability, this is seen in a more relaxed way in the consumer sector, where temperature windows are not so much of an issue.
All manufacturers of dynamic NAND storage media, including Micron, permanently switch back to TLC mode after a defined maximum number of program and erase cycles. Before that, the storage medium achieves the best values especially during short write processes that do not require the entire capacity. However, the medium is permanently slowed down after a certain usage time, which should never be ignored. Phison’s E18 masters the dynamic change of the configuration of flash blocks quite well, but it can’t outsmart physics either.
It remains to be seen when the end of the Spatium M480 Pro’s great cache performance will be reached. Real long-term tests will have to show that in the end, because unfortunately nothing is known about the Micron NAND. Thus, we gladly take note of the performance measured today, but also have to restrictively note that it will certainly be usable for longer, but never in the long run if you want to qualify as the write and erase king of large memory blocks.
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